The International Roadmap for
Devices and Systems (IRDS)

by Paolo A. Gargini, IEEE Life Fellow, I-JSAP Fellow, Chairman IRDS,
Francis Balestra (SiNANO), Director of Research CNRS,
Vice President Grenoble INP,
Director of the European SiNANO Institute,
Yoshihiro Hayashi (SDRJ), Visiting Professor,
Faculty of Science and Technology, Keio University

Introduction

The IRDS focuses on producing a roadmap of the fundamental building blocks of the electronics industry spanning from devices to systems and from systems to devices. These are the foundations of the AI-centric social-infrastructure of the IoT that will be connected via high speed network communication as illustrated in Fig. 1. The IRDS offers a 15-year outlook that allows enough time for researchers to study solutions to solve difficult problems looming 10 years ahead and beyond, while offering a series of short-term technological and system options that can come to full fruition within the next 5 to 10 years. Finally, the IRDS closely monitors advancements of the electronics industry in the next coming 5 years to verify that previously reported projections had indeed been consistent with actual technology and system actual implementations adopted in high-volume manufacturing by the electronics and semiconductor industries.

Fig. 1. IRDS provides the building blocks of the future IoT society

The 2020 IRDS predicts that many fundamental changes will occur in the next 15 years. For instance, as device scaling reaches fundamental limits around the year 2030, Moore’s Law will continue to hold by stacking multiple layers of transistors in the vertical dimension and by means of new innovative architectures. Will eventually quantum technology and algorithms allow increasing functionality per unit area to continue by allowing multiple bits to physically coexist?

1. Roadmap Methodology Background

The IRDS is the third generation of the roadmap methodology firstly empirically outlined by Gordon Moore as far back as 1965 (1). At that time he predicted that the number of transistors that could be integrated in a single die (i.e., in an integrated circuit, (IC)) will double every year for the subsequent 10 years. His prediction turned out to be correct and in 1975 he revised his prediction to a doubling of transistors every 2 years for the foreseeable future (2). He also identified three fundamental contributors to achieving these results: IC architecture, miniaturization of components and the ability to produce increasingly larger dice at low cost due to high manufacturing yields. Around that time Robert Dennard published a set of rules on how to easily predict performance of scaled down transistors (3). The semiconductor industry diligently followed these guidelines for the subsequent 15 years.

Dennard methodology held true until about 2005. Conversely, Moore’s Law still holds true to this day and it is anticipated that will continue to be valid for at least the next 10 years.

In 1991 universities, industry and government organizations in the US got together and decided to formalize in a comprehensive document the details of future trends governing the future of the semiconductor and electronics industries with a 15-year outlook. The question of this exercise was: “How long will Moore’s Law continue to be applicable?” For this purpose 11 Technology Working Groups (TWGs) were formed. The National Technology Roadmap for Semiconductors (NTRS) was published in 1992, 1994 and 1997, respectively.

By 1996 it became clear that major roadblocks were going to be encountered by the beginning of the next decade; for instance, the thickness of the gate dielectric would have been nullified by 2005 at the latest. Solving these problems required a full re-engineering of the transistor structure in a way that had been done before. This was no longer a US-only problem; it affected the entire semiconductor industry and electronics industries around the world.

To efficiently tackle this problem, the International Technology Roadmap for Semiconductors (ITRS) was formed in 1998 with participation of organizations from Europe, Japan, Korea, Taiwan and the US. An aggressive and revolutionary program to completely overall how transistors are structured and manufactured was outlined (Fig. 2).

Fig. 2. 1998ITRS proposed transistor structure

Extensive cooperation of universities, suppliers, multiple governments’ funded programs and consortia around the world led to the systematic introduction in rapid succession of strained silicon, high-k/metal-gate, FinFET in manufacturing. This effort was completed by 2011 and saved the semiconductor and the electronics industry.

2. The Continuously Evolving Supply Chain

The introduction of the personal computer (PC) in the 80s revolutionized the semiconductor industry. Until then semiconductor manufactures had sold their products to corporations that integrated different semiconductor products into unique systems (e.g., mainframe computers), that were sold or leased to other corporations. However, the diffusion of the PC quickly reached the consumer market and the advent of the Internet further popularized the adoption of notebooks as communication devices. However, consumers continually have different requirements—most of all they want new and exciting products on an almost monthly schedule never experienced before by the semiconductor industry. The combination of Intel, as the integrated device manufacturer (IDM) and Microsoft, as the almost exclusive software provider arose to the task and was able to respond to this escalating demand. Additionally, Intel dominated the PC market leaving the role of the system integrators to mere receivers of software and technology with limited choices on how to integrate the PC or notebook (e.g., screen size, amount of memory, etc.).

The introduction of the iPhone in 2007 and the introduction of the iPad in 2010 revolutionized the supply chain model even further. Apple demonstrated that system integrators could design their own products, design their own chips and have them successfully manufactured by a foundry.

In the PC-era Intel and Microsoft controlled the pace of the electronics market, in the smart phone-era the system integrators (in association with foundries) had finally regained the driver seat position controlling the growth of the electronics industry.

3. From ITRS to IRDS

In the 2013 ITRS it was anticipated that some fundamental dimensional and architectural limits were going to be reached in the not too distant future, first by memory products and then by logic products as well. In essence, increasing transistor density by making them smaller was going to become too expensive for memory manufactures due to escalating lithography costs. On the other hand, logic circuits were becoming too crowded to simultaneously accommodate for higher functional density and reduced power dissipation.

The 2013 ITRS recommendation consisted in aggressively utilizing the vertical dimension to increase the number of transistors packed per unit area (Fig. 3). Flash memory manufacturers were fast to respond to this recommendation and by 2015 new Flash products stacking tens of layers of memory cells were announced; forecasts of adding hundreds of layers as time went by were projected also. This vertical approach to increasing transistor density has become today’s reality as Flash memory products with more than 100 layers have been reported for imminent introduction.

Fig. 3. 2013ITRS proposed vertical transistor evolution

Furthermore, by 2012 it had become clear that requirements formulated by system integrators were solidly controlling designs of new semiconductor circuits. New capabilities were constantly required to be added to new custom ICs driven by consumers’ needs. As a response, the ITRS number of TWGs and roadmap chapters had grown to 17. To evolve in synchronicity with the new ecosystem the roadmap evolved and transitioned in 2014 into an interim structure under the name of “ITRS 2.0.” With this transformation the TWGs were integrated into clusters accordingly to the level of interdependence of their activities. In addition, new clusters covering subjects not considered before were formed under the new terminology of International Focus Teams (IFTs).

In the new methodology, system requirements percolated down into IC requirements and IC innovations quickly escalated up to create new options for system integrators. This transformation was completed by late 2015 and published under the name of “2015 ITRS 2.0.”

With this transformation completed the new broader mission of the roadmap going forward was sealed under a new name: International Roadmap of Devices and Systems (IRDS). The International Roadmap Committee (IRC) is composed of representatives from the European Academic and Scientific Association for NanoElectronics (SiNANO), the System and Device Roadmap of Japan (SDRJ), the IEEE Electron Devices Society (EDS), and from the IEEE Computer Society (CS).

During this transformational period, the structure of the electronics industry and the semiconductor industry had completely changed. Faced with increasing costs of research, design and manufacturing multiple companies decided to give up on manufacturing leading-edge digital semiconductors to concentrate all their resources on IC designs and, in limited cases, to still produce specialty semiconductors. Nowadays the system integrators–foundry model increasingly has replaced the IDM-system integrators model of the past decades. Under these conditions it became evident that the IRDS had evolved far beyond the initial world of semiconductors and needed to move to a much broader organization. In May 2016, IEEE adopted the IRDS under the umbrella of the Rebooting Computing Initiative (RCI) as the two organizations were serendipity complementing each other.

The System device roadmap committees of Japan (SDRJ) supported by the Japan Society of Applied Physics (JSAP), and the European SINANO institute have been actively participating in the IRDS from 2017 and 2018 respectively.

The international organizations from Japan and EU have been contributing to the IEEE IRDS^TM by jointly addressing technical topics and directions making it a true international effort. Monthly international webinars are regularly held to exchange regional information and recommendations on technical and management subjects.

4. IRDS Structure: The IFTs

1. Applications Benchmarking (AB)
   The mission of the Applications Benchmarking (AB) IFT in the IRDS is to update and identify key application drivers, and to track and roadmap the performance of these applications for the next 15 years. The output of the AB market drivers in conjunction with the drivers of the Systems and Architectures (SA) IFT, generates a cross-matrix map showing which application(s) are important or critical (gating) for each market.
2. Systems and Architecture (SA)
   The mission of the System Architecture (SA) chapter in the IRDS is to establish a top-down, system-driven 15-year roadmapping framework for key market drivers of the semiconductor industry. The SA chapter is proposing roadmaps of relevant system metrics for mobile applications, datacenter, IoT, and cyber-physical systems (CPS).
3. Outside system Connectivity (OSC)
   The mission of the OSC IFT in the IRDS consists in identifying and assessing capabilities needed to connect most elements of the Internet of Everything (IoE) and highlight technology needs and gaps. This includes supporting interconnection of a broad range of sensors, devices, and products to support information communication, processing and analysis for many applications including automobiles, aerospace, and a wide range of IoT applications for personal use, home, transportation, factory, and warehouse. Communication of data over fiber optic circuits to data centers and fiber optic communication within data centers is in scope for this chapter.
4. More Moore (MM)
   The More Moore (MM) IFT of the IRDS provides physical, electrical and reliability requirements for logic and memory technologies to sustain More Moore (Power, performance, area, cost (PPAC) scaling for big data, mobility, and cloud (IoT and server) applications and forecasted logic and memory technologies (15 years) in main-stream/high-volume manufacturing (HVM). The 2013 ITRS already anticipated that fundamental limits of 2D scaling were going to be reached for all product lines between 2015 and 2021.
   Already 72−96 layers of Flash memory cells have been demonstrated in manufacturing. It is anticipated that logic technologies will transition to 3D approaches in the next few years. These technological solutions will assure continuation of Moore’s Law for additional 10−15 years.
5. Beyond CMOS (BC)
   The goal of the Beyond CMOS (BC) IFT of the IRDS is to survey, assess, and catalog viable new information processing devices and system architectures due to their relevance on technological choices. It is also important to identify the scientific/technological challenges gating their acceptance by the semiconductor industry as having acceptable risk for further development. Another goal is to pursue long-term alternative solutions to technologies addressed in More-than-Moore (MtM) entries.
6. Cryogenics Electronics and Quantum Information Processing (CE&QIP)
   The goal of this chapter for the IRDS is to survey, catalog, and assess the status of technologies in the areas of cryogenic electronics and quantum information processing. Application drivers are identified for sufficiently developed technologies and application needs are mapped as a function of time against projected capabilities to identify challenges requiring research and development effort. Cryogenic electronics (also referred to as low-temperature electronics or cold electronics) is defined by operation at cryogenic temperatures (below −150 C or 123.15 K) and includes devices and circuits made from a variety of materials including insulators, conductors, semiconductors, superconductors, or topological materials. Existing and emerging applications are driving development of novel cryogenic electronic technologies.
   Quantum information processing is different in that it uses qubits, two-state quantum-mechanical systems that can be in coherent superpositions of both states at the same time, which can have computational advantages. Measurement of a qubit causes it to collapse to either one state or the other.
7. Packaging Integration (PI)
   The Packaging Integration (PI) focus of the IRDS is divided between the near-term assembly and packaging roadmap requirements and the introduction of many new requirements and potential solutions to meet market needs in the longer term. Packaging integration is the final manufacturing process transforming semiconductor devices into functional products for the end user. Packaging provides electrical connections for signal transmission, power input, and voltage control. It also provides solutions for thermal dissipation and the physical protection required for reliability. Heterogeneous integration of multiple technologies has become a dominant factor in the past 10 years enabling a variety of new products, especially in the mobile category.
8. Factory Integration (FI)
   The Factory Integration (FI) focus area is dedicated to ensuring that the semiconductor-manufacturing infrastructure contains the necessary components to produce items at affordable cost and high volume. Realizing the potential of Moore’s Law requires taking full advantage of device feature size reductions, new materials, yield improvement to near 100%, wafer size increases, and other manufacturing productivity improvements. This in turn requires a factory system that can fully integrate additional factory components and utilize these components collectively to deliver items that meet specifications determined by other IRDS focus areas as well as cost, volume, and yield targets.
9. Lithography (L)
   The Lithography (L) focus area of patterning technology has been high-performance logic chips, DRAM memory, and Flash memory. High performance logic chips are now the drivers for better resolution features, Extreme Ultraviolet Lithography (EUVL) is now being implemented into manufacturing for leading edge logic due to the benefits it offers in reducing development cycle and manufacturing cycle times, decreasing the numbers of patterning levels and reducing overall complexity. DRAM memory is trailing high performance logic in critical dimensions and in using EUVL. Flash memory has switched from scaling horizontally to stacking vertically and its patterning challenges relate to cost and to finding processes that reduce process steps.
10. Yield Enhancement (YE)
    The Yield Enhancement (YE) focus area is dedicated to activities ensuring that semiconductor manufacturing is optimized for production of the maximum number of functional units. Identifying, reducing, and avoiding relevant defects and contamination that can adversely affect and reduce overall product output are necessary to accomplish this goal. Yield in most industries has been defined as the number of functional and sealable products made divided by the number of products that can be potentially made. In the semiconductor industry, yield is represented by the functionality and reliability of integrated circuits produced on the wafer surfaces. During the manufacturing of ICs yield loss is caused, for example, by defects, faults, process variations, and design. The Yield chapter of the IRDS presents the current advanced and next generation future requirements for high-yielding manufacturing of More Moore as well as More than Moore products.
11. Metrology (M)
    The Metrology Chapter (M) of the IRDS identifies emerging measurement challenges from devices, systems, and integration in the semiconductor industry and describes research and development pathways for overcoming them. Metrology Chapter focused on reviewing and updating references. This includes, but is not limited to, measurement needs for extending CMOS, beyond CMOS technologies, novel communication devices, sensors and transducers, materials characterization and structure/function relationships. This also includes metrology required in research and development, and techniques providing process control in manufacturing, yield, and failure analysis.
12. Environment, Safety, Health, and Sustainability (ESH/S)
    The Environmental, Safety, Health, and Sustainability (ESH/S) chapter of the IRDS serves to provide a long-range framework and process for all key stakeholders in the semiconductor and microelectronics industry, to develop proactive technical solutions to address critical ESH/S challenges up front, without gating industry R&D, mitigating cost, ensuring business continuity, and identifying key new markets and opportunities.
13. More Than Moore (MtM)
    The More than Moore chapter of the 2020 IRDS is devoted to the incorporation into smart electronic systems of non-digital functionalities that do not necessarily scale according to Moore’s Law. These new functionalities provide additional value in the field of sensors, actuators, or power management. This functional diversification allows a number of systems to more efficient interacting with each other and also offer new ways to communicate with the outside world while minimizing energy consumption by powering the nano-systems with “free” energy harvesting.

5. Planning for the next 15 years with the IRDS

Several events are predicted by the 2020 IRDS that could lead to a yet new ecosystem of the electronics industry in the third decade of this century. However, the transition will not happen very smoothly or even at all unless action is taken immediately. The warning given by the 2020 IRDS is meant to stimulate initiation of programs in a timely manner. A few of these transition points stand out:

Most of All, Scaling Will Reach Its Limits in the Second Half of This Decade

Feature scaling has substantially contributed to increasing the number of transistors per die in accordance with Moore’s Law (1,2) since the beginning of the IC industry. Imaging of features of smaller dimensions to increase transistor density and performance has been accomplished for the past 50 years utilizing light of progressively smaller wavelength and lenses of higher numerical apertures. During this time, the exposure wavelength of lithographic equipment evolved from 436 nm to 193 nm, yielding a reduction of device features from the 10-micron range in the 1970s to tens of nanometers nowadays.

EUV imaging technology (13.5 nm) has been introduced into manufacturing in the past couple of years, after more than 20 years in development. The NA of the present equipment is 0.33 and the ultimate exposure tool with NA better than 0.5 will be introduced by 2023. The downside is that according to all experts no new cost-effective imaging technology will be available in the future. It is expected that features around 7–8 nm will be in manufacturing somewhat before 2030 but no additional feature reductions are anticipated beyond that (Fig. 4).

Fig. 4. 2020IRDS Preparing for scaling leveling off

Fear not, the game is not over! All Flash memory manufacturers are aggressively using the vertical dimension of ICs to increase the number of transistors per unit area. Logic device manufacture will follow later in the decade. Innovative architecture will continue to increase functionality. As AI technologies and architectures continue to advance in combination with leading-edge ultra-low-power semiconductor technologies, it will be possible to realize AI-equipped-cyber-physical systems to be deployed in the IoT-edge systems; eventually some of these applications will be “attached” on/in our bodies for medication and healthcare. Furthermore, a variety of quantum computing and information technologies are fighting to replace scaling—promising innovative avenues to increase functionality. The adoption of multiple bits per component will open up the 4^th dimension to increasing functionality without requirements for reducing feature size.

Read all the details of the IRDS in the currently on line issues 2016, 2017 and 2018 and the latest 2020 IRDS at the following address https://irds.ieee.org/editions and in the multiple articles coming up on this publication in the following months.

References

[1] G.E. Moore, G., “Cramming More Components onto Integrated Circuits,” Electronics, Vol. 38, No. 8, April 19, 1965.

[2] G.E. Moore., “Progress in Digital Integrated Circuits,” Plenary Address, International Electron Devices Conference, Dec 1−3, 1975, Washington, D.C.

[3] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc, “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE Journal of Solid State Circuits, Vol. SC-9, No.5, pp. 256-268, October 1974.